#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include "cydevice_trm.h"

/* LED */
#define LED__0__DR CYREG_GPIO_PRT0_DR
#define LED__0__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define LED__0__DR_INV CYREG_GPIO_PRT0_DR_INV
#define LED__0__DR_SET CYREG_GPIO_PRT0_DR_SET
#define LED__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define LED__0__HSIOM_MASK 0x0000000Fu
#define LED__0__HSIOM_SHIFT 0u
#define LED__0__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__0__INTR CYREG_GPIO_PRT0_INTR
#define LED__0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__0__INTSTAT CYREG_GPIO_PRT0_INTR
#define LED__0__MASK 0x01u
#define LED__0__PC CYREG_GPIO_PRT0_PC
#define LED__0__PC2 CYREG_GPIO_PRT0_PC2
#define LED__0__PORT 0u
#define LED__0__PS CYREG_GPIO_PRT0_PS
#define LED__0__SHIFT 0u
#define LED__1__DR CYREG_GPIO_PRT0_DR
#define LED__1__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define LED__1__DR_INV CYREG_GPIO_PRT0_DR_INV
#define LED__1__DR_SET CYREG_GPIO_PRT0_DR_SET
#define LED__1__HSIOM CYREG_HSIOM_PORT_SEL0
#define LED__1__HSIOM_MASK 0x000000F0u
#define LED__1__HSIOM_SHIFT 4u
#define LED__1__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__1__INTR CYREG_GPIO_PRT0_INTR
#define LED__1__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__1__INTSTAT CYREG_GPIO_PRT0_INTR
#define LED__1__MASK 0x02u
#define LED__1__PC CYREG_GPIO_PRT0_PC
#define LED__1__PC2 CYREG_GPIO_PRT0_PC2
#define LED__1__PORT 0u
#define LED__1__PS CYREG_GPIO_PRT0_PS
#define LED__1__SHIFT 1u
#define LED__2__DR CYREG_GPIO_PRT0_DR
#define LED__2__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define LED__2__DR_INV CYREG_GPIO_PRT0_DR_INV
#define LED__2__DR_SET CYREG_GPIO_PRT0_DR_SET
#define LED__2__HSIOM CYREG_HSIOM_PORT_SEL0
#define LED__2__HSIOM_MASK 0x00000F00u
#define LED__2__HSIOM_SHIFT 8u
#define LED__2__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__2__INTR CYREG_GPIO_PRT0_INTR
#define LED__2__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__2__INTSTAT CYREG_GPIO_PRT0_INTR
#define LED__2__MASK 0x04u
#define LED__2__PC CYREG_GPIO_PRT0_PC
#define LED__2__PC2 CYREG_GPIO_PRT0_PC2
#define LED__2__PORT 0u
#define LED__2__PS CYREG_GPIO_PRT0_PS
#define LED__2__SHIFT 2u
#define LED__3__DR CYREG_GPIO_PRT0_DR
#define LED__3__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define LED__3__DR_INV CYREG_GPIO_PRT0_DR_INV
#define LED__3__DR_SET CYREG_GPIO_PRT0_DR_SET
#define LED__3__HSIOM CYREG_HSIOM_PORT_SEL0
#define LED__3__HSIOM_MASK 0x0000F000u
#define LED__3__HSIOM_SHIFT 12u
#define LED__3__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__3__INTR CYREG_GPIO_PRT0_INTR
#define LED__3__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__3__INTSTAT CYREG_GPIO_PRT0_INTR
#define LED__3__MASK 0x08u
#define LED__3__PC CYREG_GPIO_PRT0_PC
#define LED__3__PC2 CYREG_GPIO_PRT0_PC2
#define LED__3__PORT 0u
#define LED__3__PS CYREG_GPIO_PRT0_PS
#define LED__3__SHIFT 3u
#define LED__4__DR CYREG_GPIO_PRT0_DR
#define LED__4__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define LED__4__DR_INV CYREG_GPIO_PRT0_DR_INV
#define LED__4__DR_SET CYREG_GPIO_PRT0_DR_SET
#define LED__4__HSIOM CYREG_HSIOM_PORT_SEL0
#define LED__4__HSIOM_MASK 0x000F0000u
#define LED__4__HSIOM_SHIFT 16u
#define LED__4__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__4__INTR CYREG_GPIO_PRT0_INTR
#define LED__4__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__4__INTSTAT CYREG_GPIO_PRT0_INTR
#define LED__4__MASK 0x10u
#define LED__4__PC CYREG_GPIO_PRT0_PC
#define LED__4__PC2 CYREG_GPIO_PRT0_PC2
#define LED__4__PORT 0u
#define LED__4__PS CYREG_GPIO_PRT0_PS
#define LED__4__SHIFT 4u
#define LED__5__DR CYREG_GPIO_PRT0_DR
#define LED__5__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define LED__5__DR_INV CYREG_GPIO_PRT0_DR_INV
#define LED__5__DR_SET CYREG_GPIO_PRT0_DR_SET
#define LED__5__HSIOM CYREG_HSIOM_PORT_SEL0
#define LED__5__HSIOM_MASK 0x00F00000u
#define LED__5__HSIOM_SHIFT 20u
#define LED__5__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__5__INTR CYREG_GPIO_PRT0_INTR
#define LED__5__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__5__INTSTAT CYREG_GPIO_PRT0_INTR
#define LED__5__MASK 0x20u
#define LED__5__PC CYREG_GPIO_PRT0_PC
#define LED__5__PC2 CYREG_GPIO_PRT0_PC2
#define LED__5__PORT 0u
#define LED__5__PS CYREG_GPIO_PRT0_PS
#define LED__5__SHIFT 5u
#define LED__6__DR CYREG_GPIO_PRT0_DR
#define LED__6__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define LED__6__DR_INV CYREG_GPIO_PRT0_DR_INV
#define LED__6__DR_SET CYREG_GPIO_PRT0_DR_SET
#define LED__6__HSIOM CYREG_HSIOM_PORT_SEL0
#define LED__6__HSIOM_MASK 0x0F000000u
#define LED__6__HSIOM_SHIFT 24u
#define LED__6__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__6__INTR CYREG_GPIO_PRT0_INTR
#define LED__6__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__6__INTSTAT CYREG_GPIO_PRT0_INTR
#define LED__6__MASK 0x40u
#define LED__6__PC CYREG_GPIO_PRT0_PC
#define LED__6__PC2 CYREG_GPIO_PRT0_PC2
#define LED__6__PORT 0u
#define LED__6__PS CYREG_GPIO_PRT0_PS
#define LED__6__SHIFT 6u
#define LED__7__DR CYREG_GPIO_PRT0_DR
#define LED__7__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define LED__7__DR_INV CYREG_GPIO_PRT0_DR_INV
#define LED__7__DR_SET CYREG_GPIO_PRT0_DR_SET
#define LED__7__HSIOM CYREG_HSIOM_PORT_SEL0
#define LED__7__HSIOM_MASK 0xF0000000u
#define LED__7__HSIOM_SHIFT 28u
#define LED__7__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__7__INTR CYREG_GPIO_PRT0_INTR
#define LED__7__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__7__INTSTAT CYREG_GPIO_PRT0_INTR
#define LED__7__MASK 0x80u
#define LED__7__PC CYREG_GPIO_PRT0_PC
#define LED__7__PC2 CYREG_GPIO_PRT0_PC2
#define LED__7__PORT 0u
#define LED__7__PS CYREG_GPIO_PRT0_PS
#define LED__7__SHIFT 7u
#define LED__DR CYREG_GPIO_PRT0_DR
#define LED__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define LED__DR_INV CYREG_GPIO_PRT0_DR_INV
#define LED__DR_SET CYREG_GPIO_PRT0_DR_SET
#define LED__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__INTR CYREG_GPIO_PRT0_INTR
#define LED__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define LED__INTSTAT CYREG_GPIO_PRT0_INTR
#define LED__MASK 0xFFu
#define LED__PC CYREG_GPIO_PRT0_PC
#define LED__PC2 CYREG_GPIO_PRT0_PC2
#define LED__PORT 0u
#define LED__PS CYREG_GPIO_PRT0_PS
#define LED__SHIFT 0u

/* UART_rx */
#define UART_rx__0__DR CYREG_GPIO_PRT1_DR
#define UART_rx__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define UART_rx__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define UART_rx__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define UART_rx__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define UART_rx__0__HSIOM_GPIO 0u
#define UART_rx__0__HSIOM_I2C 14u
#define UART_rx__0__HSIOM_I2C_SCL 14u
#define UART_rx__0__HSIOM_MASK 0x0000000Fu
#define UART_rx__0__HSIOM_SHIFT 0u
#define UART_rx__0__HSIOM_SPI 15u
#define UART_rx__0__HSIOM_SPI_MOSI 15u
#define UART_rx__0__HSIOM_UART 9u
#define UART_rx__0__HSIOM_UART_RX 9u
#define UART_rx__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_rx__0__INTR CYREG_GPIO_PRT1_INTR
#define UART_rx__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_rx__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define UART_rx__0__MASK 0x01u
#define UART_rx__0__PC CYREG_GPIO_PRT1_PC
#define UART_rx__0__PC2 CYREG_GPIO_PRT1_PC2
#define UART_rx__0__PORT 1u
#define UART_rx__0__PS CYREG_GPIO_PRT1_PS
#define UART_rx__0__SHIFT 0u
#define UART_rx__DR CYREG_GPIO_PRT1_DR
#define UART_rx__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define UART_rx__DR_INV CYREG_GPIO_PRT1_DR_INV
#define UART_rx__DR_SET CYREG_GPIO_PRT1_DR_SET
#define UART_rx__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_rx__INTR CYREG_GPIO_PRT1_INTR
#define UART_rx__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_rx__INTSTAT CYREG_GPIO_PRT1_INTR
#define UART_rx__MASK 0x01u
#define UART_rx__PC CYREG_GPIO_PRT1_PC
#define UART_rx__PC2 CYREG_GPIO_PRT1_PC2
#define UART_rx__PORT 1u
#define UART_rx__PS CYREG_GPIO_PRT1_PS
#define UART_rx__SHIFT 0u

/* UART_SCB */
#define UART_SCB__CTRL CYREG_SCB0_CTRL
#define UART_SCB__EZ_DATA0 CYREG_SCB0_EZ_DATA0
#define UART_SCB__EZ_DATA1 CYREG_SCB0_EZ_DATA1
#define UART_SCB__EZ_DATA10 CYREG_SCB0_EZ_DATA10
#define UART_SCB__EZ_DATA11 CYREG_SCB0_EZ_DATA11
#define UART_SCB__EZ_DATA12 CYREG_SCB0_EZ_DATA12
#define UART_SCB__EZ_DATA13 CYREG_SCB0_EZ_DATA13
#define UART_SCB__EZ_DATA14 CYREG_SCB0_EZ_DATA14
#define UART_SCB__EZ_DATA15 CYREG_SCB0_EZ_DATA15
#define UART_SCB__EZ_DATA16 CYREG_SCB0_EZ_DATA16
#define UART_SCB__EZ_DATA17 CYREG_SCB0_EZ_DATA17
#define UART_SCB__EZ_DATA18 CYREG_SCB0_EZ_DATA18
#define UART_SCB__EZ_DATA19 CYREG_SCB0_EZ_DATA19
#define UART_SCB__EZ_DATA2 CYREG_SCB0_EZ_DATA2
#define UART_SCB__EZ_DATA20 CYREG_SCB0_EZ_DATA20
#define UART_SCB__EZ_DATA21 CYREG_SCB0_EZ_DATA21
#define UART_SCB__EZ_DATA22 CYREG_SCB0_EZ_DATA22
#define UART_SCB__EZ_DATA23 CYREG_SCB0_EZ_DATA23
#define UART_SCB__EZ_DATA24 CYREG_SCB0_EZ_DATA24
#define UART_SCB__EZ_DATA25 CYREG_SCB0_EZ_DATA25
#define UART_SCB__EZ_DATA26 CYREG_SCB0_EZ_DATA26
#define UART_SCB__EZ_DATA27 CYREG_SCB0_EZ_DATA27
#define UART_SCB__EZ_DATA28 CYREG_SCB0_EZ_DATA28
#define UART_SCB__EZ_DATA29 CYREG_SCB0_EZ_DATA29
#define UART_SCB__EZ_DATA3 CYREG_SCB0_EZ_DATA3
#define UART_SCB__EZ_DATA30 CYREG_SCB0_EZ_DATA30
#define UART_SCB__EZ_DATA31 CYREG_SCB0_EZ_DATA31
#define UART_SCB__EZ_DATA4 CYREG_SCB0_EZ_DATA4
#define UART_SCB__EZ_DATA5 CYREG_SCB0_EZ_DATA5
#define UART_SCB__EZ_DATA6 CYREG_SCB0_EZ_DATA6
#define UART_SCB__EZ_DATA7 CYREG_SCB0_EZ_DATA7
#define UART_SCB__EZ_DATA8 CYREG_SCB0_EZ_DATA8
#define UART_SCB__EZ_DATA9 CYREG_SCB0_EZ_DATA9
#define UART_SCB__I2C_CFG CYREG_SCB0_I2C_CFG
#define UART_SCB__I2C_CTRL CYREG_SCB0_I2C_CTRL
#define UART_SCB__I2C_M_CMD CYREG_SCB0_I2C_M_CMD
#define UART_SCB__I2C_S_CMD CYREG_SCB0_I2C_S_CMD
#define UART_SCB__I2C_STATUS CYREG_SCB0_I2C_STATUS
#define UART_SCB__INTR_CAUSE CYREG_SCB0_INTR_CAUSE
#define UART_SCB__INTR_I2C_EC CYREG_SCB0_INTR_I2C_EC
#define UART_SCB__INTR_I2C_EC_MASK CYREG_SCB0_INTR_I2C_EC_MASK
#define UART_SCB__INTR_I2C_EC_MASKED CYREG_SCB0_INTR_I2C_EC_MASKED
#define UART_SCB__INTR_M CYREG_SCB0_INTR_M
#define UART_SCB__INTR_M_MASK CYREG_SCB0_INTR_M_MASK
#define UART_SCB__INTR_M_MASKED CYREG_SCB0_INTR_M_MASKED
#define UART_SCB__INTR_M_SET CYREG_SCB0_INTR_M_SET
#define UART_SCB__INTR_RX CYREG_SCB0_INTR_RX
#define UART_SCB__INTR_RX_MASK CYREG_SCB0_INTR_RX_MASK
#define UART_SCB__INTR_RX_MASKED CYREG_SCB0_INTR_RX_MASKED
#define UART_SCB__INTR_RX_SET CYREG_SCB0_INTR_RX_SET
#define UART_SCB__INTR_S CYREG_SCB0_INTR_S
#define UART_SCB__INTR_S_MASK CYREG_SCB0_INTR_S_MASK
#define UART_SCB__INTR_S_MASKED CYREG_SCB0_INTR_S_MASKED
#define UART_SCB__INTR_S_SET CYREG_SCB0_INTR_S_SET
#define UART_SCB__INTR_SPI_EC CYREG_SCB0_INTR_SPI_EC
#define UART_SCB__INTR_SPI_EC_MASK CYREG_SCB0_INTR_SPI_EC_MASK
#define UART_SCB__INTR_SPI_EC_MASKED CYREG_SCB0_INTR_SPI_EC_MASKED
#define UART_SCB__INTR_TX CYREG_SCB0_INTR_TX
#define UART_SCB__INTR_TX_MASK CYREG_SCB0_INTR_TX_MASK
#define UART_SCB__INTR_TX_MASKED CYREG_SCB0_INTR_TX_MASKED
#define UART_SCB__INTR_TX_SET CYREG_SCB0_INTR_TX_SET
#define UART_SCB__RX_CTRL CYREG_SCB0_RX_CTRL
#define UART_SCB__RX_FIFO_CTRL CYREG_SCB0_RX_FIFO_CTRL
#define UART_SCB__RX_FIFO_RD CYREG_SCB0_RX_FIFO_RD
#define UART_SCB__RX_FIFO_RD_SILENT CYREG_SCB0_RX_FIFO_RD_SILENT
#define UART_SCB__RX_FIFO_STATUS CYREG_SCB0_RX_FIFO_STATUS
#define UART_SCB__RX_MATCH CYREG_SCB0_RX_MATCH
#define UART_SCB__SPI_CTRL CYREG_SCB0_SPI_CTRL
#define UART_SCB__SPI_STATUS CYREG_SCB0_SPI_STATUS
#define UART_SCB__SS0_POSISTION 0u
#define UART_SCB__SS1_POSISTION 1u
#define UART_SCB__SS2_POSISTION 2u
#define UART_SCB__SS3_POSISTION 3u
#define UART_SCB__STATUS CYREG_SCB0_STATUS
#define UART_SCB__TX_CTRL CYREG_SCB0_TX_CTRL
#define UART_SCB__TX_FIFO_CTRL CYREG_SCB0_TX_FIFO_CTRL
#define UART_SCB__TX_FIFO_STATUS CYREG_SCB0_TX_FIFO_STATUS
#define UART_SCB__TX_FIFO_WR CYREG_SCB0_TX_FIFO_WR
#define UART_SCB__UART_CTRL CYREG_SCB0_UART_CTRL
#define UART_SCB__UART_FLOW_CTRL CYREG_SCB0_UART_FLOW_CTRL
#define UART_SCB__UART_RX_CTRL CYREG_SCB0_UART_RX_CTRL
#define UART_SCB__UART_RX_STATUS CYREG_SCB0_UART_RX_STATUS
#define UART_SCB__UART_TX_CTRL CYREG_SCB0_UART_TX_CTRL

/* UART_SCB_IRQ */
#define UART_SCB_IRQ__INTC_CLR_EN_REG CYREG_CM0P_ICER
#define UART_SCB_IRQ__INTC_CLR_PD_REG CYREG_CM0P_ICPR
#define UART_SCB_IRQ__INTC_MASK 0x80u
#define UART_SCB_IRQ__INTC_NUMBER 7u
#define UART_SCB_IRQ__INTC_PRIOR_MASK 0xC0000000u
#define UART_SCB_IRQ__INTC_PRIOR_NUM 2u
#define UART_SCB_IRQ__INTC_PRIOR_REG CYREG_CM0P_IPR1
#define UART_SCB_IRQ__INTC_SET_EN_REG CYREG_CM0P_ISER
#define UART_SCB_IRQ__INTC_SET_PD_REG CYREG_CM0P_ISPR

/* UART_SCBCLK */
#define UART_SCBCLK__CTRL_REGISTER CYREG_PERI_PCLK_CTL0
#define UART_SCBCLK__DIV_ID 0x00000080u
#define UART_SCBCLK__DIV_REGISTER CYREG_PERI_DIV_16_5_CTL0
#define UART_SCBCLK__FRAC_MASK 0x000000F8u
#define UART_SCBCLK__PA_DIV_ID 0x000000FFu

/* UART_tx */
#define UART_tx__0__DR CYREG_GPIO_PRT1_DR
#define UART_tx__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define UART_tx__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define UART_tx__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define UART_tx__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define UART_tx__0__HSIOM_GPIO 0u
#define UART_tx__0__HSIOM_I2C 14u
#define UART_tx__0__HSIOM_I2C_SDA 14u
#define UART_tx__0__HSIOM_MASK 0x000000F0u
#define UART_tx__0__HSIOM_SHIFT 4u
#define UART_tx__0__HSIOM_SPI 15u
#define UART_tx__0__HSIOM_SPI_MISO 15u
#define UART_tx__0__HSIOM_UART 9u
#define UART_tx__0__HSIOM_UART_TX 9u
#define UART_tx__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_tx__0__INTR CYREG_GPIO_PRT1_INTR
#define UART_tx__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_tx__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define UART_tx__0__MASK 0x02u
#define UART_tx__0__PC CYREG_GPIO_PRT1_PC
#define UART_tx__0__PC2 CYREG_GPIO_PRT1_PC2
#define UART_tx__0__PORT 1u
#define UART_tx__0__PS CYREG_GPIO_PRT1_PS
#define UART_tx__0__SHIFT 1u
#define UART_tx__DR CYREG_GPIO_PRT1_DR
#define UART_tx__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define UART_tx__DR_INV CYREG_GPIO_PRT1_DR_INV
#define UART_tx__DR_SET CYREG_GPIO_PRT1_DR_SET
#define UART_tx__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_tx__INTR CYREG_GPIO_PRT1_INTR
#define UART_tx__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define UART_tx__INTSTAT CYREG_GPIO_PRT1_INTR
#define UART_tx__MASK 0x02u
#define UART_tx__PC CYREG_GPIO_PRT1_PC
#define UART_tx__PC2 CYREG_GPIO_PRT1_PC2
#define UART_tx__PORT 1u
#define UART_tx__PS CYREG_GPIO_PRT1_PS
#define UART_tx__SHIFT 1u

/* Clock_2 */
#define Clock_2__CTRL_REGISTER CYREG_PERI_PCLK_CTL6
#define Clock_2__DIV_ID 0x00000044u
#define Clock_2__DIV_REGISTER CYREG_PERI_DIV_16_CTL4
#define Clock_2__PA_DIV_ID 0x000000FFu

/* CapSense_AdcInput */
#define CapSense_AdcInput__0__DR CYREG_GPIO_PRT2_DR
#define CapSense_AdcInput__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define CapSense_AdcInput__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define CapSense_AdcInput__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define CapSense_AdcInput__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define CapSense_AdcInput__0__HSIOM_MASK 0x00F00000u
#define CapSense_AdcInput__0__HSIOM_SHIFT 20u
#define CapSense_AdcInput__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define CapSense_AdcInput__0__INTR CYREG_GPIO_PRT2_INTR
#define CapSense_AdcInput__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define CapSense_AdcInput__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define CapSense_AdcInput__0__MASK 0x20u
#define CapSense_AdcInput__0__PC CYREG_GPIO_PRT2_PC
#define CapSense_AdcInput__0__PC2 CYREG_GPIO_PRT2_PC2
#define CapSense_AdcInput__0__PORT 2u
#define CapSense_AdcInput__0__PS CYREG_GPIO_PRT2_PS
#define CapSense_AdcInput__0__SHIFT 5u
#define CapSense_AdcInput__1__DR CYREG_GPIO_PRT3_DR
#define CapSense_AdcInput__1__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CapSense_AdcInput__1__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CapSense_AdcInput__1__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CapSense_AdcInput__1__HSIOM CYREG_HSIOM_PORT_SEL3
#define CapSense_AdcInput__1__HSIOM_MASK 0x00F00000u
#define CapSense_AdcInput__1__HSIOM_SHIFT 20u
#define CapSense_AdcInput__1__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CapSense_AdcInput__1__INTR CYREG_GPIO_PRT3_INTR
#define CapSense_AdcInput__1__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CapSense_AdcInput__1__INTSTAT CYREG_GPIO_PRT3_INTR
#define CapSense_AdcInput__1__MASK 0x20u
#define CapSense_AdcInput__1__PC CYREG_GPIO_PRT3_PC
#define CapSense_AdcInput__1__PC2 CYREG_GPIO_PRT3_PC2
#define CapSense_AdcInput__1__PORT 3u
#define CapSense_AdcInput__1__PS CYREG_GPIO_PRT3_PS
#define CapSense_AdcInput__1__SHIFT 5u
#define CapSense_AdcInput__Ch0__DR CYREG_GPIO_PRT2_DR
#define CapSense_AdcInput__Ch0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define CapSense_AdcInput__Ch0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define CapSense_AdcInput__Ch0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define CapSense_AdcInput__Ch0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define CapSense_AdcInput__Ch0__INTR CYREG_GPIO_PRT2_INTR
#define CapSense_AdcInput__Ch0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define CapSense_AdcInput__Ch0__INTSTAT CYREG_GPIO_PRT2_INTR
#define CapSense_AdcInput__Ch0__MASK 0x20u
#define CapSense_AdcInput__Ch0__PC CYREG_GPIO_PRT2_PC
#define CapSense_AdcInput__Ch0__PC2 CYREG_GPIO_PRT2_PC2
#define CapSense_AdcInput__Ch0__PORT 2u
#define CapSense_AdcInput__Ch0__PS CYREG_GPIO_PRT2_PS
#define CapSense_AdcInput__Ch0__SHIFT 5u
#define CapSense_AdcInput__Ch1__DR CYREG_GPIO_PRT3_DR
#define CapSense_AdcInput__Ch1__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CapSense_AdcInput__Ch1__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CapSense_AdcInput__Ch1__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CapSense_AdcInput__Ch1__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CapSense_AdcInput__Ch1__INTR CYREG_GPIO_PRT3_INTR
#define CapSense_AdcInput__Ch1__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CapSense_AdcInput__Ch1__INTSTAT CYREG_GPIO_PRT3_INTR
#define CapSense_AdcInput__Ch1__MASK 0x20u
#define CapSense_AdcInput__Ch1__PC CYREG_GPIO_PRT3_PC
#define CapSense_AdcInput__Ch1__PC2 CYREG_GPIO_PRT3_PC2
#define CapSense_AdcInput__Ch1__PORT 3u
#define CapSense_AdcInput__Ch1__PS CYREG_GPIO_PRT3_PS
#define CapSense_AdcInput__Ch1__SHIFT 5u

/* CapSense_Cmod */
#define CapSense_Cmod__0__DR CYREG_GPIO_PRT4_DR
#define CapSense_Cmod__0__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define CapSense_Cmod__0__DR_INV CYREG_GPIO_PRT4_DR_INV
#define CapSense_Cmod__0__DR_SET CYREG_GPIO_PRT4_DR_SET
#define CapSense_Cmod__0__HSIOM CYREG_HSIOM_PORT_SEL4
#define CapSense_Cmod__0__HSIOM_MASK 0x00000F00u
#define CapSense_Cmod__0__HSIOM_SHIFT 8u
#define CapSense_Cmod__0__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Cmod__0__INTR CYREG_GPIO_PRT4_INTR
#define CapSense_Cmod__0__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Cmod__0__INTSTAT CYREG_GPIO_PRT4_INTR
#define CapSense_Cmod__0__MASK 0x04u
#define CapSense_Cmod__0__PC CYREG_GPIO_PRT4_PC
#define CapSense_Cmod__0__PC2 CYREG_GPIO_PRT4_PC2
#define CapSense_Cmod__0__PORT 4u
#define CapSense_Cmod__0__PS CYREG_GPIO_PRT4_PS
#define CapSense_Cmod__0__SHIFT 2u
#define CapSense_Cmod__Cmod__DR CYREG_GPIO_PRT4_DR
#define CapSense_Cmod__Cmod__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define CapSense_Cmod__Cmod__DR_INV CYREG_GPIO_PRT4_DR_INV
#define CapSense_Cmod__Cmod__DR_SET CYREG_GPIO_PRT4_DR_SET
#define CapSense_Cmod__Cmod__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Cmod__Cmod__INTR CYREG_GPIO_PRT4_INTR
#define CapSense_Cmod__Cmod__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Cmod__Cmod__INTSTAT CYREG_GPIO_PRT4_INTR
#define CapSense_Cmod__Cmod__MASK 0x04u
#define CapSense_Cmod__Cmod__PC CYREG_GPIO_PRT4_PC
#define CapSense_Cmod__Cmod__PC2 CYREG_GPIO_PRT4_PC2
#define CapSense_Cmod__Cmod__PORT 4u
#define CapSense_Cmod__Cmod__PS CYREG_GPIO_PRT4_PS
#define CapSense_Cmod__Cmod__SHIFT 2u
#define CapSense_Cmod__DR CYREG_GPIO_PRT4_DR
#define CapSense_Cmod__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define CapSense_Cmod__DR_INV CYREG_GPIO_PRT4_DR_INV
#define CapSense_Cmod__DR_SET CYREG_GPIO_PRT4_DR_SET
#define CapSense_Cmod__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Cmod__INTR CYREG_GPIO_PRT4_INTR
#define CapSense_Cmod__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Cmod__INTSTAT CYREG_GPIO_PRT4_INTR
#define CapSense_Cmod__MASK 0x04u
#define CapSense_Cmod__PC CYREG_GPIO_PRT4_PC
#define CapSense_Cmod__PC2 CYREG_GPIO_PRT4_PC2
#define CapSense_Cmod__PORT 4u
#define CapSense_Cmod__PS CYREG_GPIO_PRT4_PS
#define CapSense_Cmod__SHIFT 2u

/* CapSense_CSD */
#define CapSense_CSD__ADC_CTL CYREG_CSD_ADC_CTL
#define CapSense_CSD__CMOD_PAD 1u
#define CapSense_CSD__CSD_CONFIG CYREG_CSD_CONFIG
#define CapSense_CSD__CSD_INTR CYREG_CSD_INTR
#define CapSense_CSD__CSD_INTR_SET CYREG_CSD_INTR_SET
#define CapSense_CSD__CSD_NUMBER 0u
#define CapSense_CSD__CSD_STATUS CYREG_CSD_STATUS
#define CapSense_CSD__CSDCMP CYREG_CSD_CSDCMP
#define CapSense_CSD__CSH_TANK_PAD 2u
#define CapSense_CSD__CSHIELD_PAD 4u
#define CapSense_CSD__DEDICATED_IO CapSense_CSD__CMOD_PAD
#define CapSense_CSD__HSCMP CYREG_CSD_HSCMP
#define CapSense_CSD__INTR_MASK CYREG_CSD_INTR_MASK
#define CapSense_CSD__REFGEN CYREG_CSD_REFGEN
#define CapSense_CSD__RESULT_VAL1 CYREG_CSD_RESULT_VAL1
#define CapSense_CSD__RESULT_VAL2 CYREG_CSD_RESULT_VAL2
#define CapSense_CSD__SENSE_DUTY CYREG_CSD_SENSE_DUTY
#define CapSense_CSD__SENSE_PERIOD CYREG_CSD_SENSE_PERIOD
#define CapSense_CSD__SEQ_INIT_CNT CYREG_CSD_SEQ_INIT_CNT
#define CapSense_CSD__SEQ_NORM_CNT CYREG_CSD_SEQ_NORM_CNT
#define CapSense_CSD__SEQ_START CYREG_CSD_SEQ_START
#define CapSense_CSD__SEQ_TIME CYREG_CSD_SEQ_TIME
#define CapSense_CSD__SW_AMUXBUF_SEL CYREG_CSD_SW_AMUXBUF_SEL
#define CapSense_CSD__SW_BYP_SEL CYREG_CSD_SW_BYP_SEL
#define CapSense_CSD__SW_CMP_N_SEL CYREG_CSD_SW_CMP_N_SEL
#define CapSense_CSD__SW_CMP_P_SEL CYREG_CSD_SW_CMP_P_SEL
#define CapSense_CSD__SW_DSI_SEL CYREG_CSD_SW_DSI_SEL
#define CapSense_CSD__SW_FW_MOD_SEL CYREG_CSD_SW_FW_MOD_SEL
#define CapSense_CSD__SW_FW_TANK_SEL CYREG_CSD_SW_FW_TANK_SEL
#define CapSense_CSD__SW_HS_N_SEL CYREG_CSD_SW_HS_N_SEL
#define CapSense_CSD__SW_HS_P_SEL CYREG_CSD_SW_HS_P_SEL
#define CapSense_CSD__SW_REFGEN_SEL CYREG_CSD_SW_REFGEN_SEL
#define CapSense_CSD__SW_RES CYREG_CSD_SW_RES
#define CapSense_CSD__SW_SHIELD_SEL CYREG_CSD_SW_SHIELD_SEL

/* CapSense_IDACComp */
#define CapSense_IDACComp__CONFIG CYREG_CSD_CONFIG
#define CapSense_IDACComp__IDAC CYREG_CSD_IDACB
#define CapSense_IDACComp__POSITION 1u

/* CapSense_IDACMod */
#define CapSense_IDACMod__CONFIG CYREG_CSD_CONFIG
#define CapSense_IDACMod__IDAC CYREG_CSD_IDACA
#define CapSense_IDACMod__POSITION 0u

/* CapSense_ISR */
#define CapSense_ISR__INTC_CLR_EN_REG CYREG_CM0P_ICER
#define CapSense_ISR__INTC_CLR_PD_REG CYREG_CM0P_ICPR
#define CapSense_ISR__INTC_MASK 0x400u
#define CapSense_ISR__INTC_NUMBER 10u
#define CapSense_ISR__INTC_PRIOR_MASK 0xC00000u
#define CapSense_ISR__INTC_PRIOR_NUM 0u
#define CapSense_ISR__INTC_PRIOR_REG CYREG_CM0P_IPR2
#define CapSense_ISR__INTC_SET_EN_REG CYREG_CM0P_ISER
#define CapSense_ISR__INTC_SET_PD_REG CYREG_CM0P_ISPR

/* CapSense_ModClk */
#define CapSense_ModClk__CTRL_REGISTER CYREG_PERI_PCLK_CTL2
#define CapSense_ModClk__DIV_ID 0x00000040u
#define CapSense_ModClk__DIV_REGISTER CYREG_PERI_DIV_16_CTL0
#define CapSense_ModClk__PA_DIV_ID 0x000000FFu

/* CapSense_Shield */
#define CapSense_Shield__0__DR CYREG_GPIO_PRT1_DR
#define CapSense_Shield__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define CapSense_Shield__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define CapSense_Shield__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define CapSense_Shield__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define CapSense_Shield__0__HSIOM_MASK 0x0F000000u
#define CapSense_Shield__0__HSIOM_SHIFT 24u
#define CapSense_Shield__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Shield__0__INTR CYREG_GPIO_PRT1_INTR
#define CapSense_Shield__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Shield__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define CapSense_Shield__0__MASK 0x40u
#define CapSense_Shield__0__PC CYREG_GPIO_PRT1_PC
#define CapSense_Shield__0__PC2 CYREG_GPIO_PRT1_PC2
#define CapSense_Shield__0__PORT 1u
#define CapSense_Shield__0__PS CYREG_GPIO_PRT1_PS
#define CapSense_Shield__0__SHIFT 6u
#define CapSense_Shield__DR CYREG_GPIO_PRT1_DR
#define CapSense_Shield__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define CapSense_Shield__DR_INV CYREG_GPIO_PRT1_DR_INV
#define CapSense_Shield__DR_SET CYREG_GPIO_PRT1_DR_SET
#define CapSense_Shield__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Shield__INTR CYREG_GPIO_PRT1_INTR
#define CapSense_Shield__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Shield__INTSTAT CYREG_GPIO_PRT1_INTR
#define CapSense_Shield__MASK 0x40u
#define CapSense_Shield__PC CYREG_GPIO_PRT1_PC
#define CapSense_Shield__PC2 CYREG_GPIO_PRT1_PC2
#define CapSense_Shield__PORT 1u
#define CapSense_Shield__PS CYREG_GPIO_PRT1_PS
#define CapSense_Shield__Shield__DR CYREG_GPIO_PRT1_DR
#define CapSense_Shield__Shield__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define CapSense_Shield__Shield__DR_INV CYREG_GPIO_PRT1_DR_INV
#define CapSense_Shield__Shield__DR_SET CYREG_GPIO_PRT1_DR_SET
#define CapSense_Shield__Shield__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Shield__Shield__INTR CYREG_GPIO_PRT1_INTR
#define CapSense_Shield__Shield__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Shield__Shield__INTSTAT CYREG_GPIO_PRT1_INTR
#define CapSense_Shield__Shield__MASK 0x40u
#define CapSense_Shield__Shield__PC CYREG_GPIO_PRT1_PC
#define CapSense_Shield__Shield__PC2 CYREG_GPIO_PRT1_PC2
#define CapSense_Shield__Shield__PORT 1u
#define CapSense_Shield__Shield__PS CYREG_GPIO_PRT1_PS
#define CapSense_Shield__Shield__SHIFT 6u
#define CapSense_Shield__SHIFT 6u

/* CapSense_Sns */
#define CapSense_Sns__0__DR CYREG_GPIO_PRT1_DR
#define CapSense_Sns__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define CapSense_Sns__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define CapSense_Sns__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define CapSense_Sns__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define CapSense_Sns__0__HSIOM_MASK 0x00F00000u
#define CapSense_Sns__0__HSIOM_SHIFT 20u
#define CapSense_Sns__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__0__INTR CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__0__MASK 0x20u
#define CapSense_Sns__0__PC CYREG_GPIO_PRT1_PC
#define CapSense_Sns__0__PC2 CYREG_GPIO_PRT1_PC2
#define CapSense_Sns__0__PORT 1u
#define CapSense_Sns__0__PS CYREG_GPIO_PRT1_PS
#define CapSense_Sns__0__SHIFT 5u
#define CapSense_Sns__1__DR CYREG_GPIO_PRT1_DR
#define CapSense_Sns__1__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define CapSense_Sns__1__DR_INV CYREG_GPIO_PRT1_DR_INV
#define CapSense_Sns__1__DR_SET CYREG_GPIO_PRT1_DR_SET
#define CapSense_Sns__1__HSIOM CYREG_HSIOM_PORT_SEL1
#define CapSense_Sns__1__HSIOM_MASK 0x000F0000u
#define CapSense_Sns__1__HSIOM_SHIFT 16u
#define CapSense_Sns__1__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__1__INTR CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__1__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__1__INTSTAT CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__1__MASK 0x10u
#define CapSense_Sns__1__PC CYREG_GPIO_PRT1_PC
#define CapSense_Sns__1__PC2 CYREG_GPIO_PRT1_PC2
#define CapSense_Sns__1__PORT 1u
#define CapSense_Sns__1__PS CYREG_GPIO_PRT1_PS
#define CapSense_Sns__1__SHIFT 4u
#define CapSense_Sns__2__DR CYREG_GPIO_PRT1_DR
#define CapSense_Sns__2__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define CapSense_Sns__2__DR_INV CYREG_GPIO_PRT1_DR_INV
#define CapSense_Sns__2__DR_SET CYREG_GPIO_PRT1_DR_SET
#define CapSense_Sns__2__HSIOM CYREG_HSIOM_PORT_SEL1
#define CapSense_Sns__2__HSIOM_MASK 0x0000F000u
#define CapSense_Sns__2__HSIOM_SHIFT 12u
#define CapSense_Sns__2__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__2__INTR CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__2__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__2__INTSTAT CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__2__MASK 0x08u
#define CapSense_Sns__2__PC CYREG_GPIO_PRT1_PC
#define CapSense_Sns__2__PC2 CYREG_GPIO_PRT1_PC2
#define CapSense_Sns__2__PORT 1u
#define CapSense_Sns__2__PS CYREG_GPIO_PRT1_PS
#define CapSense_Sns__2__SHIFT 3u
#define CapSense_Sns__3__DR CYREG_GPIO_PRT1_DR
#define CapSense_Sns__3__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define CapSense_Sns__3__DR_INV CYREG_GPIO_PRT1_DR_INV
#define CapSense_Sns__3__DR_SET CYREG_GPIO_PRT1_DR_SET
#define CapSense_Sns__3__HSIOM CYREG_HSIOM_PORT_SEL1
#define CapSense_Sns__3__HSIOM_MASK 0x00000F00u
#define CapSense_Sns__3__HSIOM_SHIFT 8u
#define CapSense_Sns__3__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__3__INTR CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__3__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__3__INTSTAT CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__3__MASK 0x04u
#define CapSense_Sns__3__PC CYREG_GPIO_PRT1_PC
#define CapSense_Sns__3__PC2 CYREG_GPIO_PRT1_PC2
#define CapSense_Sns__3__PORT 1u
#define CapSense_Sns__3__PS CYREG_GPIO_PRT1_PS
#define CapSense_Sns__3__SHIFT 2u
#define CapSense_Sns__4__DR CYREG_GPIO_PRT3_DR
#define CapSense_Sns__4__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CapSense_Sns__4__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CapSense_Sns__4__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CapSense_Sns__4__HSIOM CYREG_HSIOM_PORT_SEL3
#define CapSense_Sns__4__HSIOM_MASK 0x0F000000u
#define CapSense_Sns__4__HSIOM_SHIFT 24u
#define CapSense_Sns__4__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CapSense_Sns__4__INTR CYREG_GPIO_PRT3_INTR
#define CapSense_Sns__4__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CapSense_Sns__4__INTSTAT CYREG_GPIO_PRT3_INTR
#define CapSense_Sns__4__MASK 0x40u
#define CapSense_Sns__4__PC CYREG_GPIO_PRT3_PC
#define CapSense_Sns__4__PC2 CYREG_GPIO_PRT3_PC2
#define CapSense_Sns__4__PORT 3u
#define CapSense_Sns__4__PS CYREG_GPIO_PRT3_PS
#define CapSense_Sns__4__SHIFT 6u
#define CapSense_Sns__5__DR CYREG_GPIO_PRT3_DR
#define CapSense_Sns__5__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CapSense_Sns__5__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CapSense_Sns__5__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CapSense_Sns__5__HSIOM CYREG_HSIOM_PORT_SEL3
#define CapSense_Sns__5__HSIOM_MASK 0xF0000000u
#define CapSense_Sns__5__HSIOM_SHIFT 28u
#define CapSense_Sns__5__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CapSense_Sns__5__INTR CYREG_GPIO_PRT3_INTR
#define CapSense_Sns__5__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CapSense_Sns__5__INTSTAT CYREG_GPIO_PRT3_INTR
#define CapSense_Sns__5__MASK 0x80u
#define CapSense_Sns__5__PC CYREG_GPIO_PRT3_PC
#define CapSense_Sns__5__PC2 CYREG_GPIO_PRT3_PC2
#define CapSense_Sns__5__PORT 3u
#define CapSense_Sns__5__PS CYREG_GPIO_PRT3_PS
#define CapSense_Sns__5__SHIFT 7u
#define CapSense_Sns__6__DR CYREG_GPIO_PRT4_DR
#define CapSense_Sns__6__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define CapSense_Sns__6__DR_INV CYREG_GPIO_PRT4_DR_INV
#define CapSense_Sns__6__DR_SET CYREG_GPIO_PRT4_DR_SET
#define CapSense_Sns__6__HSIOM CYREG_HSIOM_PORT_SEL4
#define CapSense_Sns__6__HSIOM_MASK 0x0000000Fu
#define CapSense_Sns__6__HSIOM_SHIFT 0u
#define CapSense_Sns__6__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Sns__6__INTR CYREG_GPIO_PRT4_INTR
#define CapSense_Sns__6__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Sns__6__INTSTAT CYREG_GPIO_PRT4_INTR
#define CapSense_Sns__6__MASK 0x01u
#define CapSense_Sns__6__PC CYREG_GPIO_PRT4_PC
#define CapSense_Sns__6__PC2 CYREG_GPIO_PRT4_PC2
#define CapSense_Sns__6__PORT 4u
#define CapSense_Sns__6__PS CYREG_GPIO_PRT4_PS
#define CapSense_Sns__6__SHIFT 0u
#define CapSense_Sns__Button0_Sns0__DR CYREG_GPIO_PRT1_DR
#define CapSense_Sns__Button0_Sns0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define CapSense_Sns__Button0_Sns0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define CapSense_Sns__Button0_Sns0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define CapSense_Sns__Button0_Sns0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__Button0_Sns0__INTR CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__Button0_Sns0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__Button0_Sns0__INTSTAT CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__Button0_Sns0__MASK 0x20u
#define CapSense_Sns__Button0_Sns0__PC CYREG_GPIO_PRT1_PC
#define CapSense_Sns__Button0_Sns0__PC2 CYREG_GPIO_PRT1_PC2
#define CapSense_Sns__Button0_Sns0__PORT 1u
#define CapSense_Sns__Button0_Sns0__PS CYREG_GPIO_PRT1_PS
#define CapSense_Sns__Button0_Sns0__SHIFT 5u
#define CapSense_Sns__Button1_Sns0__DR CYREG_GPIO_PRT1_DR
#define CapSense_Sns__Button1_Sns0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define CapSense_Sns__Button1_Sns0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define CapSense_Sns__Button1_Sns0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define CapSense_Sns__Button1_Sns0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__Button1_Sns0__INTR CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__Button1_Sns0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__Button1_Sns0__INTSTAT CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__Button1_Sns0__MASK 0x10u
#define CapSense_Sns__Button1_Sns0__PC CYREG_GPIO_PRT1_PC
#define CapSense_Sns__Button1_Sns0__PC2 CYREG_GPIO_PRT1_PC2
#define CapSense_Sns__Button1_Sns0__PORT 1u
#define CapSense_Sns__Button1_Sns0__PS CYREG_GPIO_PRT1_PS
#define CapSense_Sns__Button1_Sns0__SHIFT 4u
#define CapSense_Sns__Button2_Sns0__DR CYREG_GPIO_PRT1_DR
#define CapSense_Sns__Button2_Sns0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define CapSense_Sns__Button2_Sns0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define CapSense_Sns__Button2_Sns0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define CapSense_Sns__Button2_Sns0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__Button2_Sns0__INTR CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__Button2_Sns0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__Button2_Sns0__INTSTAT CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__Button2_Sns0__MASK 0x08u
#define CapSense_Sns__Button2_Sns0__PC CYREG_GPIO_PRT1_PC
#define CapSense_Sns__Button2_Sns0__PC2 CYREG_GPIO_PRT1_PC2
#define CapSense_Sns__Button2_Sns0__PORT 1u
#define CapSense_Sns__Button2_Sns0__PS CYREG_GPIO_PRT1_PS
#define CapSense_Sns__Button2_Sns0__SHIFT 3u
#define CapSense_Sns__Button3_Sns0__DR CYREG_GPIO_PRT1_DR
#define CapSense_Sns__Button3_Sns0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define CapSense_Sns__Button3_Sns0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define CapSense_Sns__Button3_Sns0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define CapSense_Sns__Button3_Sns0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__Button3_Sns0__INTR CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__Button3_Sns0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define CapSense_Sns__Button3_Sns0__INTSTAT CYREG_GPIO_PRT1_INTR
#define CapSense_Sns__Button3_Sns0__MASK 0x04u
#define CapSense_Sns__Button3_Sns0__PC CYREG_GPIO_PRT1_PC
#define CapSense_Sns__Button3_Sns0__PC2 CYREG_GPIO_PRT1_PC2
#define CapSense_Sns__Button3_Sns0__PORT 1u
#define CapSense_Sns__Button3_Sns0__PS CYREG_GPIO_PRT1_PS
#define CapSense_Sns__Button3_Sns0__SHIFT 2u
#define CapSense_Sns__Button4_Sns0__DR CYREG_GPIO_PRT3_DR
#define CapSense_Sns__Button4_Sns0__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CapSense_Sns__Button4_Sns0__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CapSense_Sns__Button4_Sns0__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CapSense_Sns__Button4_Sns0__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CapSense_Sns__Button4_Sns0__INTR CYREG_GPIO_PRT3_INTR
#define CapSense_Sns__Button4_Sns0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CapSense_Sns__Button4_Sns0__INTSTAT CYREG_GPIO_PRT3_INTR
#define CapSense_Sns__Button4_Sns0__MASK 0x40u
#define CapSense_Sns__Button4_Sns0__PC CYREG_GPIO_PRT3_PC
#define CapSense_Sns__Button4_Sns0__PC2 CYREG_GPIO_PRT3_PC2
#define CapSense_Sns__Button4_Sns0__PORT 3u
#define CapSense_Sns__Button4_Sns0__PS CYREG_GPIO_PRT3_PS
#define CapSense_Sns__Button4_Sns0__SHIFT 6u
#define CapSense_Sns__Button5_Sns0__DR CYREG_GPIO_PRT3_DR
#define CapSense_Sns__Button5_Sns0__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CapSense_Sns__Button5_Sns0__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CapSense_Sns__Button5_Sns0__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CapSense_Sns__Button5_Sns0__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CapSense_Sns__Button5_Sns0__INTR CYREG_GPIO_PRT3_INTR
#define CapSense_Sns__Button5_Sns0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CapSense_Sns__Button5_Sns0__INTSTAT CYREG_GPIO_PRT3_INTR
#define CapSense_Sns__Button5_Sns0__MASK 0x80u
#define CapSense_Sns__Button5_Sns0__PC CYREG_GPIO_PRT3_PC
#define CapSense_Sns__Button5_Sns0__PC2 CYREG_GPIO_PRT3_PC2
#define CapSense_Sns__Button5_Sns0__PORT 3u
#define CapSense_Sns__Button5_Sns0__PS CYREG_GPIO_PRT3_PS
#define CapSense_Sns__Button5_Sns0__SHIFT 7u
#define CapSense_Sns__Button6_Sns0__DR CYREG_GPIO_PRT4_DR
#define CapSense_Sns__Button6_Sns0__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define CapSense_Sns__Button6_Sns0__DR_INV CYREG_GPIO_PRT4_DR_INV
#define CapSense_Sns__Button6_Sns0__DR_SET CYREG_GPIO_PRT4_DR_SET
#define CapSense_Sns__Button6_Sns0__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Sns__Button6_Sns0__INTR CYREG_GPIO_PRT4_INTR
#define CapSense_Sns__Button6_Sns0__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define CapSense_Sns__Button6_Sns0__INTSTAT CYREG_GPIO_PRT4_INTR
#define CapSense_Sns__Button6_Sns0__MASK 0x01u
#define CapSense_Sns__Button6_Sns0__PC CYREG_GPIO_PRT4_PC
#define CapSense_Sns__Button6_Sns0__PC2 CYREG_GPIO_PRT4_PC2
#define CapSense_Sns__Button6_Sns0__PORT 4u
#define CapSense_Sns__Button6_Sns0__PS CYREG_GPIO_PRT4_PS
#define CapSense_Sns__Button6_Sns0__SHIFT 0u

/* PWM_Beep_cy_m0s8_tcpwm_1 */
#define PWM_Beep_cy_m0s8_tcpwm_1__CC CYREG_TCPWM_CNT0_CC
#define PWM_Beep_cy_m0s8_tcpwm_1__CC_BUFF CYREG_TCPWM_CNT0_CC_BUFF
#define PWM_Beep_cy_m0s8_tcpwm_1__COUNTER CYREG_TCPWM_CNT0_COUNTER
#define PWM_Beep_cy_m0s8_tcpwm_1__CTRL CYREG_TCPWM_CNT0_CTRL
#define PWM_Beep_cy_m0s8_tcpwm_1__INTR CYREG_TCPWM_CNT0_INTR
#define PWM_Beep_cy_m0s8_tcpwm_1__INTR_MASK CYREG_TCPWM_CNT0_INTR_MASK
#define PWM_Beep_cy_m0s8_tcpwm_1__INTR_MASKED CYREG_TCPWM_CNT0_INTR_MASKED
#define PWM_Beep_cy_m0s8_tcpwm_1__INTR_SET CYREG_TCPWM_CNT0_INTR_SET
#define PWM_Beep_cy_m0s8_tcpwm_1__PERIOD CYREG_TCPWM_CNT0_PERIOD
#define PWM_Beep_cy_m0s8_tcpwm_1__PERIOD_BUFF CYREG_TCPWM_CNT0_PERIOD_BUFF
#define PWM_Beep_cy_m0s8_tcpwm_1__STATUS CYREG_TCPWM_CNT0_STATUS
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMD CYREG_TCPWM_CMD
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK 0x01u
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT 0u
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK 0x100u
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT 8u
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK 0x1000000u
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT 24u
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK 0x10000u
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT 16u
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CTRL CYREG_TCPWM_CTRL
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK 0x01u
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT 0u
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE CYREG_TCPWM_INTR_CAUSE
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK 0x01u
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT 0u
#define PWM_Beep_cy_m0s8_tcpwm_1__TCPWM_NUMBER 0u
#define PWM_Beep_cy_m0s8_tcpwm_1__TR_CTRL0 CYREG_TCPWM_CNT0_TR_CTRL0
#define PWM_Beep_cy_m0s8_tcpwm_1__TR_CTRL1 CYREG_TCPWM_CNT0_TR_CTRL1
#define PWM_Beep_cy_m0s8_tcpwm_1__TR_CTRL2 CYREG_TCPWM_CNT0_TR_CTRL2

/* Pin_Beep */
#define Pin_Beep__0__DR CYREG_GPIO_PRT2_DR
#define Pin_Beep__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Pin_Beep__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Pin_Beep__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Pin_Beep__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin_Beep__0__HSIOM_MASK 0x000F0000u
#define Pin_Beep__0__HSIOM_SHIFT 16u
#define Pin_Beep__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_Beep__0__INTR CYREG_GPIO_PRT2_INTR
#define Pin_Beep__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_Beep__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define Pin_Beep__0__MASK 0x10u
#define Pin_Beep__0__PC CYREG_GPIO_PRT2_PC
#define Pin_Beep__0__PC2 CYREG_GPIO_PRT2_PC2
#define Pin_Beep__0__PORT 2u
#define Pin_Beep__0__PS CYREG_GPIO_PRT2_PS
#define Pin_Beep__0__SHIFT 4u
#define Pin_Beep__DR CYREG_GPIO_PRT2_DR
#define Pin_Beep__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Pin_Beep__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Pin_Beep__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Pin_Beep__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_Beep__INTR CYREG_GPIO_PRT2_INTR
#define Pin_Beep__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_Beep__INTSTAT CYREG_GPIO_PRT2_INTR
#define Pin_Beep__MASK 0x10u
#define Pin_Beep__PC CYREG_GPIO_PRT2_PC
#define Pin_Beep__PC2 CYREG_GPIO_PRT2_PC2
#define Pin_Beep__PORT 2u
#define Pin_Beep__PS CYREG_GPIO_PRT2_PS
#define Pin_Beep__SHIFT 4u

/* Radar_EN */
#define Radar_EN__0__DR CYREG_GPIO_PRT4_DR
#define Radar_EN__0__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define Radar_EN__0__DR_INV CYREG_GPIO_PRT4_DR_INV
#define Radar_EN__0__DR_SET CYREG_GPIO_PRT4_DR_SET
#define Radar_EN__0__HSIOM CYREG_HSIOM_PORT_SEL4
#define Radar_EN__0__HSIOM_MASK 0x0000F000u
#define Radar_EN__0__HSIOM_SHIFT 12u
#define Radar_EN__0__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define Radar_EN__0__INTR CYREG_GPIO_PRT4_INTR
#define Radar_EN__0__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define Radar_EN__0__INTSTAT CYREG_GPIO_PRT4_INTR
#define Radar_EN__0__MASK 0x08u
#define Radar_EN__0__PC CYREG_GPIO_PRT4_PC
#define Radar_EN__0__PC2 CYREG_GPIO_PRT4_PC2
#define Radar_EN__0__PORT 4u
#define Radar_EN__0__PS CYREG_GPIO_PRT4_PS
#define Radar_EN__0__SHIFT 3u
#define Radar_EN__DR CYREG_GPIO_PRT4_DR
#define Radar_EN__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define Radar_EN__DR_INV CYREG_GPIO_PRT4_DR_INV
#define Radar_EN__DR_SET CYREG_GPIO_PRT4_DR_SET
#define Radar_EN__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define Radar_EN__INTR CYREG_GPIO_PRT4_INTR
#define Radar_EN__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define Radar_EN__INTSTAT CYREG_GPIO_PRT4_INTR
#define Radar_EN__MASK 0x08u
#define Radar_EN__PC CYREG_GPIO_PRT4_PC
#define Radar_EN__PC2 CYREG_GPIO_PRT4_PC2
#define Radar_EN__PORT 4u
#define Radar_EN__PS CYREG_GPIO_PRT4_PS
#define Radar_EN__SHIFT 3u

/* Timer8_1_cy_m0s8_tcpwm_1 */
#define Timer8_1_cy_m0s8_tcpwm_1__CC CYREG_TCPWM_CNT3_CC
#define Timer8_1_cy_m0s8_tcpwm_1__CC_BUFF CYREG_TCPWM_CNT3_CC_BUFF
#define Timer8_1_cy_m0s8_tcpwm_1__COUNTER CYREG_TCPWM_CNT3_COUNTER
#define Timer8_1_cy_m0s8_tcpwm_1__CTRL CYREG_TCPWM_CNT3_CTRL
#define Timer8_1_cy_m0s8_tcpwm_1__INTR CYREG_TCPWM_CNT3_INTR
#define Timer8_1_cy_m0s8_tcpwm_1__INTR_MASK CYREG_TCPWM_CNT3_INTR_MASK
#define Timer8_1_cy_m0s8_tcpwm_1__INTR_MASKED CYREG_TCPWM_CNT3_INTR_MASKED
#define Timer8_1_cy_m0s8_tcpwm_1__INTR_SET CYREG_TCPWM_CNT3_INTR_SET
#define Timer8_1_cy_m0s8_tcpwm_1__PERIOD CYREG_TCPWM_CNT3_PERIOD
#define Timer8_1_cy_m0s8_tcpwm_1__PERIOD_BUFF CYREG_TCPWM_CNT3_PERIOD_BUFF
#define Timer8_1_cy_m0s8_tcpwm_1__STATUS CYREG_TCPWM_CNT3_STATUS
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMD CYREG_TCPWM_CMD
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK 0x08u
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT 3u
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK 0x800u
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT 11u
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK 0x8000000u
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT 27u
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK 0x80000u
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT 19u
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CTRL CYREG_TCPWM_CTRL
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK 0x08u
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT 3u
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE CYREG_TCPWM_INTR_CAUSE
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK 0x08u
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT 3u
#define Timer8_1_cy_m0s8_tcpwm_1__TCPWM_NUMBER 3u
#define Timer8_1_cy_m0s8_tcpwm_1__TR_CTRL0 CYREG_TCPWM_CNT3_TR_CTRL0
#define Timer8_1_cy_m0s8_tcpwm_1__TR_CTRL1 CYREG_TCPWM_CNT3_TR_CTRL1
#define Timer8_1_cy_m0s8_tcpwm_1__TR_CTRL2 CYREG_TCPWM_CNT3_TR_CTRL2

/* Timer8_1_ISR */
#define Timer8_1_ISR__INTC_CLR_EN_REG CYREG_CM0P_ICER
#define Timer8_1_ISR__INTC_CLR_PD_REG CYREG_CM0P_ICPR
#define Timer8_1_ISR__INTC_MASK 0x4000u
#define Timer8_1_ISR__INTC_NUMBER 14u
#define Timer8_1_ISR__INTC_PRIOR_MASK 0xC00000u
#define Timer8_1_ISR__INTC_PRIOR_NUM 1u
#define Timer8_1_ISR__INTC_PRIOR_REG CYREG_CM0P_IPR3
#define Timer8_1_ISR__INTC_SET_EN_REG CYREG_CM0P_ISER
#define Timer8_1_ISR__INTC_SET_PD_REG CYREG_CM0P_ISPR

/* InputZero */
#define InputZero__0__DR CYREG_GPIO_PRT1_DR
#define InputZero__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define InputZero__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define InputZero__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define InputZero__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define InputZero__0__HSIOM_MASK 0xF0000000u
#define InputZero__0__HSIOM_SHIFT 28u
#define InputZero__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define InputZero__0__INTR CYREG_GPIO_PRT1_INTR
#define InputZero__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define InputZero__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define InputZero__0__MASK 0x80u
#define InputZero__0__PC CYREG_GPIO_PRT1_PC
#define InputZero__0__PC2 CYREG_GPIO_PRT1_PC2
#define InputZero__0__PORT 1u
#define InputZero__0__PS CYREG_GPIO_PRT1_PS
#define InputZero__0__SHIFT 7u
#define InputZero__DR CYREG_GPIO_PRT1_DR
#define InputZero__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define InputZero__DR_INV CYREG_GPIO_PRT1_DR_INV
#define InputZero__DR_SET CYREG_GPIO_PRT1_DR_SET
#define InputZero__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define InputZero__INTR CYREG_GPIO_PRT1_INTR
#define InputZero__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define InputZero__INTSTAT CYREG_GPIO_PRT1_INTR
#define InputZero__MASK 0x80u
#define InputZero__PC CYREG_GPIO_PRT1_PC
#define InputZero__PC2 CYREG_GPIO_PRT1_PC2
#define InputZero__PORT 1u
#define InputZero__PS CYREG_GPIO_PRT1_PS
#define InputZero__SHIFT 7u

/* PWM_Local_cy_m0s8_tcpwm_1 */
#define PWM_Local_cy_m0s8_tcpwm_1__CC CYREG_TCPWM_CNT4_CC
#define PWM_Local_cy_m0s8_tcpwm_1__CC_BUFF CYREG_TCPWM_CNT4_CC_BUFF
#define PWM_Local_cy_m0s8_tcpwm_1__COUNTER CYREG_TCPWM_CNT4_COUNTER
#define PWM_Local_cy_m0s8_tcpwm_1__CTRL CYREG_TCPWM_CNT4_CTRL
#define PWM_Local_cy_m0s8_tcpwm_1__INTR CYREG_TCPWM_CNT4_INTR
#define PWM_Local_cy_m0s8_tcpwm_1__INTR_MASK CYREG_TCPWM_CNT4_INTR_MASK
#define PWM_Local_cy_m0s8_tcpwm_1__INTR_MASKED CYREG_TCPWM_CNT4_INTR_MASKED
#define PWM_Local_cy_m0s8_tcpwm_1__INTR_SET CYREG_TCPWM_CNT4_INTR_SET
#define PWM_Local_cy_m0s8_tcpwm_1__PERIOD CYREG_TCPWM_CNT4_PERIOD
#define PWM_Local_cy_m0s8_tcpwm_1__PERIOD_BUFF CYREG_TCPWM_CNT4_PERIOD_BUFF
#define PWM_Local_cy_m0s8_tcpwm_1__STATUS CYREG_TCPWM_CNT4_STATUS
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMD CYREG_TCPWM_CMD
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK 0x10u
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT 4u
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK 0x1000u
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT 12u
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK 0x10000000u
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT 28u
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK 0x100000u
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT 20u
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CTRL CYREG_TCPWM_CTRL
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK 0x10u
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT 4u
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE CYREG_TCPWM_INTR_CAUSE
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK 0x10u
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT 4u
#define PWM_Local_cy_m0s8_tcpwm_1__TCPWM_NUMBER 4u
#define PWM_Local_cy_m0s8_tcpwm_1__TR_CTRL0 CYREG_TCPWM_CNT4_TR_CTRL0
#define PWM_Local_cy_m0s8_tcpwm_1__TR_CTRL1 CYREG_TCPWM_CNT4_TR_CTRL1
#define PWM_Local_cy_m0s8_tcpwm_1__TR_CTRL2 CYREG_TCPWM_CNT4_TR_CTRL2

/* PWM_Night_cy_m0s8_tcpwm_1 */
#define PWM_Night_cy_m0s8_tcpwm_1__CC CYREG_TCPWM_CNT2_CC
#define PWM_Night_cy_m0s8_tcpwm_1__CC_BUFF CYREG_TCPWM_CNT2_CC_BUFF
#define PWM_Night_cy_m0s8_tcpwm_1__COUNTER CYREG_TCPWM_CNT2_COUNTER
#define PWM_Night_cy_m0s8_tcpwm_1__CTRL CYREG_TCPWM_CNT2_CTRL
#define PWM_Night_cy_m0s8_tcpwm_1__INTR CYREG_TCPWM_CNT2_INTR
#define PWM_Night_cy_m0s8_tcpwm_1__INTR_MASK CYREG_TCPWM_CNT2_INTR_MASK
#define PWM_Night_cy_m0s8_tcpwm_1__INTR_MASKED CYREG_TCPWM_CNT2_INTR_MASKED
#define PWM_Night_cy_m0s8_tcpwm_1__INTR_SET CYREG_TCPWM_CNT2_INTR_SET
#define PWM_Night_cy_m0s8_tcpwm_1__PERIOD CYREG_TCPWM_CNT2_PERIOD
#define PWM_Night_cy_m0s8_tcpwm_1__PERIOD_BUFF CYREG_TCPWM_CNT2_PERIOD_BUFF
#define PWM_Night_cy_m0s8_tcpwm_1__STATUS CYREG_TCPWM_CNT2_STATUS
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMD CYREG_TCPWM_CMD
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK 0x04u
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT 2u
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK 0x400u
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT 10u
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK 0x4000000u
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT 26u
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK 0x40000u
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT 18u
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CTRL CYREG_TCPWM_CTRL
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK 0x04u
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT 2u
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE CYREG_TCPWM_INTR_CAUSE
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK 0x04u
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT 2u
#define PWM_Night_cy_m0s8_tcpwm_1__TCPWM_NUMBER 2u
#define PWM_Night_cy_m0s8_tcpwm_1__TR_CTRL0 CYREG_TCPWM_CNT2_TR_CTRL0
#define PWM_Night_cy_m0s8_tcpwm_1__TR_CTRL1 CYREG_TCPWM_CNT2_TR_CTRL1
#define PWM_Night_cy_m0s8_tcpwm_1__TR_CTRL2 CYREG_TCPWM_CNT2_TR_CTRL2

/* Pin_Local */
#define Pin_Local__0__DR CYREG_GPIO_PRT2_DR
#define Pin_Local__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Pin_Local__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Pin_Local__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Pin_Local__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin_Local__0__HSIOM_MASK 0x0000000Fu
#define Pin_Local__0__HSIOM_SHIFT 0u
#define Pin_Local__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_Local__0__INTR CYREG_GPIO_PRT2_INTR
#define Pin_Local__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_Local__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define Pin_Local__0__MASK 0x01u
#define Pin_Local__0__PC CYREG_GPIO_PRT2_PC
#define Pin_Local__0__PC2 CYREG_GPIO_PRT2_PC2
#define Pin_Local__0__PORT 2u
#define Pin_Local__0__PS CYREG_GPIO_PRT2_PS
#define Pin_Local__0__SHIFT 0u
#define Pin_Local__DR CYREG_GPIO_PRT2_DR
#define Pin_Local__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Pin_Local__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Pin_Local__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Pin_Local__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_Local__INTR CYREG_GPIO_PRT2_INTR
#define Pin_Local__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_Local__INTSTAT CYREG_GPIO_PRT2_INTR
#define Pin_Local__MASK 0x01u
#define Pin_Local__PC CYREG_GPIO_PRT2_PC
#define Pin_Local__PC2 CYREG_GPIO_PRT2_PC2
#define Pin_Local__PORT 2u
#define Pin_Local__PS CYREG_GPIO_PRT2_PS
#define Pin_Local__SHIFT 0u

/* Pin_Night */
#define Pin_Night__0__DR CYREG_GPIO_PRT3_DR
#define Pin_Night__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define Pin_Night__0__DR_INV CYREG_GPIO_PRT3_DR_INV
#define Pin_Night__0__DR_SET CYREG_GPIO_PRT3_DR_SET
#define Pin_Night__0__HSIOM CYREG_HSIOM_PORT_SEL3
#define Pin_Night__0__HSIOM_MASK 0x000F0000u
#define Pin_Night__0__HSIOM_SHIFT 16u
#define Pin_Night__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define Pin_Night__0__INTR CYREG_GPIO_PRT3_INTR
#define Pin_Night__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define Pin_Night__0__INTSTAT CYREG_GPIO_PRT3_INTR
#define Pin_Night__0__MASK 0x10u
#define Pin_Night__0__PC CYREG_GPIO_PRT3_PC
#define Pin_Night__0__PC2 CYREG_GPIO_PRT3_PC2
#define Pin_Night__0__PORT 3u
#define Pin_Night__0__PS CYREG_GPIO_PRT3_PS
#define Pin_Night__0__SHIFT 4u
#define Pin_Night__DR CYREG_GPIO_PRT3_DR
#define Pin_Night__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define Pin_Night__DR_INV CYREG_GPIO_PRT3_DR_INV
#define Pin_Night__DR_SET CYREG_GPIO_PRT3_DR_SET
#define Pin_Night__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define Pin_Night__INTR CYREG_GPIO_PRT3_INTR
#define Pin_Night__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define Pin_Night__INTSTAT CYREG_GPIO_PRT3_INTR
#define Pin_Night__MASK 0x10u
#define Pin_Night__PC CYREG_GPIO_PRT3_PC
#define Pin_Night__PC2 CYREG_GPIO_PRT3_PC2
#define Pin_Night__PORT 3u
#define Pin_Night__PS CYREG_GPIO_PRT3_PS
#define Pin_Night__SHIFT 4u

/* RELAY_ST1 */
#define RELAY_ST1__0__DR CYREG_GPIO_PRT2_DR
#define RELAY_ST1__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define RELAY_ST1__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define RELAY_ST1__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define RELAY_ST1__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define RELAY_ST1__0__HSIOM_MASK 0x0000F000u
#define RELAY_ST1__0__HSIOM_SHIFT 12u
#define RELAY_ST1__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_ST1__0__INTR CYREG_GPIO_PRT2_INTR
#define RELAY_ST1__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_ST1__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define RELAY_ST1__0__MASK 0x08u
#define RELAY_ST1__0__PC CYREG_GPIO_PRT2_PC
#define RELAY_ST1__0__PC2 CYREG_GPIO_PRT2_PC2
#define RELAY_ST1__0__PORT 2u
#define RELAY_ST1__0__PS CYREG_GPIO_PRT2_PS
#define RELAY_ST1__0__SHIFT 3u
#define RELAY_ST1__DR CYREG_GPIO_PRT2_DR
#define RELAY_ST1__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define RELAY_ST1__DR_INV CYREG_GPIO_PRT2_DR_INV
#define RELAY_ST1__DR_SET CYREG_GPIO_PRT2_DR_SET
#define RELAY_ST1__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_ST1__INTR CYREG_GPIO_PRT2_INTR
#define RELAY_ST1__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_ST1__INTSTAT CYREG_GPIO_PRT2_INTR
#define RELAY_ST1__MASK 0x08u
#define RELAY_ST1__PC CYREG_GPIO_PRT2_PC
#define RELAY_ST1__PC2 CYREG_GPIO_PRT2_PC2
#define RELAY_ST1__PORT 2u
#define RELAY_ST1__PS CYREG_GPIO_PRT2_PS
#define RELAY_ST1__SHIFT 3u

/* RELAY_ST2 */
#define RELAY_ST2__0__DR CYREG_GPIO_PRT3_DR
#define RELAY_ST2__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define RELAY_ST2__0__DR_INV CYREG_GPIO_PRT3_DR_INV
#define RELAY_ST2__0__DR_SET CYREG_GPIO_PRT3_DR_SET
#define RELAY_ST2__0__HSIOM CYREG_HSIOM_PORT_SEL3
#define RELAY_ST2__0__HSIOM_MASK 0x000000F0u
#define RELAY_ST2__0__HSIOM_SHIFT 4u
#define RELAY_ST2__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define RELAY_ST2__0__INTR CYREG_GPIO_PRT3_INTR
#define RELAY_ST2__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define RELAY_ST2__0__INTSTAT CYREG_GPIO_PRT3_INTR
#define RELAY_ST2__0__MASK 0x02u
#define RELAY_ST2__0__PC CYREG_GPIO_PRT3_PC
#define RELAY_ST2__0__PC2 CYREG_GPIO_PRT3_PC2
#define RELAY_ST2__0__PORT 3u
#define RELAY_ST2__0__PS CYREG_GPIO_PRT3_PS
#define RELAY_ST2__0__SHIFT 1u
#define RELAY_ST2__DR CYREG_GPIO_PRT3_DR
#define RELAY_ST2__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define RELAY_ST2__DR_INV CYREG_GPIO_PRT3_DR_INV
#define RELAY_ST2__DR_SET CYREG_GPIO_PRT3_DR_SET
#define RELAY_ST2__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define RELAY_ST2__INTR CYREG_GPIO_PRT3_INTR
#define RELAY_ST2__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define RELAY_ST2__INTSTAT CYREG_GPIO_PRT3_INTR
#define RELAY_ST2__MASK 0x02u
#define RELAY_ST2__PC CYREG_GPIO_PRT3_PC
#define RELAY_ST2__PC2 CYREG_GPIO_PRT3_PC2
#define RELAY_ST2__PORT 3u
#define RELAY_ST2__PS CYREG_GPIO_PRT3_PS
#define RELAY_ST2__SHIFT 1u

/* RELAY_ST3 */
#define RELAY_ST3__0__DR CYREG_GPIO_PRT2_DR
#define RELAY_ST3__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define RELAY_ST3__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define RELAY_ST3__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define RELAY_ST3__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define RELAY_ST3__0__HSIOM_MASK 0xF0000000u
#define RELAY_ST3__0__HSIOM_SHIFT 28u
#define RELAY_ST3__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_ST3__0__INTR CYREG_GPIO_PRT2_INTR
#define RELAY_ST3__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_ST3__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define RELAY_ST3__0__MASK 0x80u
#define RELAY_ST3__0__PC CYREG_GPIO_PRT2_PC
#define RELAY_ST3__0__PC2 CYREG_GPIO_PRT2_PC2
#define RELAY_ST3__0__PORT 2u
#define RELAY_ST3__0__PS CYREG_GPIO_PRT2_PS
#define RELAY_ST3__0__SHIFT 7u
#define RELAY_ST3__DR CYREG_GPIO_PRT2_DR
#define RELAY_ST3__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define RELAY_ST3__DR_INV CYREG_GPIO_PRT2_DR_INV
#define RELAY_ST3__DR_SET CYREG_GPIO_PRT2_DR_SET
#define RELAY_ST3__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_ST3__INTR CYREG_GPIO_PRT2_INTR
#define RELAY_ST3__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_ST3__INTSTAT CYREG_GPIO_PRT2_INTR
#define RELAY_ST3__MASK 0x80u
#define RELAY_ST3__PC CYREG_GPIO_PRT2_PC
#define RELAY_ST3__PC2 CYREG_GPIO_PRT2_PC2
#define RELAY_ST3__PORT 2u
#define RELAY_ST3__PS CYREG_GPIO_PRT2_PS
#define RELAY_ST3__SHIFT 7u

/* RELAY_SW1 */
#define RELAY_SW1__0__DR CYREG_GPIO_PRT3_DR
#define RELAY_SW1__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define RELAY_SW1__0__DR_INV CYREG_GPIO_PRT3_DR_INV
#define RELAY_SW1__0__DR_SET CYREG_GPIO_PRT3_DR_SET
#define RELAY_SW1__0__HSIOM CYREG_HSIOM_PORT_SEL3
#define RELAY_SW1__0__HSIOM_MASK 0x0000000Fu
#define RELAY_SW1__0__HSIOM_SHIFT 0u
#define RELAY_SW1__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define RELAY_SW1__0__INTR CYREG_GPIO_PRT3_INTR
#define RELAY_SW1__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define RELAY_SW1__0__INTSTAT CYREG_GPIO_PRT3_INTR
#define RELAY_SW1__0__MASK 0x01u
#define RELAY_SW1__0__PC CYREG_GPIO_PRT3_PC
#define RELAY_SW1__0__PC2 CYREG_GPIO_PRT3_PC2
#define RELAY_SW1__0__PORT 3u
#define RELAY_SW1__0__PS CYREG_GPIO_PRT3_PS
#define RELAY_SW1__0__SHIFT 0u
#define RELAY_SW1__DR CYREG_GPIO_PRT3_DR
#define RELAY_SW1__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define RELAY_SW1__DR_INV CYREG_GPIO_PRT3_DR_INV
#define RELAY_SW1__DR_SET CYREG_GPIO_PRT3_DR_SET
#define RELAY_SW1__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define RELAY_SW1__INTR CYREG_GPIO_PRT3_INTR
#define RELAY_SW1__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define RELAY_SW1__INTSTAT CYREG_GPIO_PRT3_INTR
#define RELAY_SW1__MASK 0x01u
#define RELAY_SW1__PC CYREG_GPIO_PRT3_PC
#define RELAY_SW1__PC2 CYREG_GPIO_PRT3_PC2
#define RELAY_SW1__PORT 3u
#define RELAY_SW1__PS CYREG_GPIO_PRT3_PS
#define RELAY_SW1__SHIFT 0u

/* RELAY_SW2 */
#define RELAY_SW2__0__DR CYREG_GPIO_PRT2_DR
#define RELAY_SW2__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define RELAY_SW2__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define RELAY_SW2__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define RELAY_SW2__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define RELAY_SW2__0__HSIOM_MASK 0x000000F0u
#define RELAY_SW2__0__HSIOM_SHIFT 4u
#define RELAY_SW2__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_SW2__0__INTR CYREG_GPIO_PRT2_INTR
#define RELAY_SW2__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_SW2__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define RELAY_SW2__0__MASK 0x02u
#define RELAY_SW2__0__PC CYREG_GPIO_PRT2_PC
#define RELAY_SW2__0__PC2 CYREG_GPIO_PRT2_PC2
#define RELAY_SW2__0__PORT 2u
#define RELAY_SW2__0__PS CYREG_GPIO_PRT2_PS
#define RELAY_SW2__0__SHIFT 1u
#define RELAY_SW2__DR CYREG_GPIO_PRT2_DR
#define RELAY_SW2__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define RELAY_SW2__DR_INV CYREG_GPIO_PRT2_DR_INV
#define RELAY_SW2__DR_SET CYREG_GPIO_PRT2_DR_SET
#define RELAY_SW2__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_SW2__INTR CYREG_GPIO_PRT2_INTR
#define RELAY_SW2__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_SW2__INTSTAT CYREG_GPIO_PRT2_INTR
#define RELAY_SW2__MASK 0x02u
#define RELAY_SW2__PC CYREG_GPIO_PRT2_PC
#define RELAY_SW2__PC2 CYREG_GPIO_PRT2_PC2
#define RELAY_SW2__PORT 2u
#define RELAY_SW2__PS CYREG_GPIO_PRT2_PS
#define RELAY_SW2__SHIFT 1u

/* RELAY_SW3 */
#define RELAY_SW3__0__DR CYREG_GPIO_PRT2_DR
#define RELAY_SW3__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define RELAY_SW3__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define RELAY_SW3__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define RELAY_SW3__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define RELAY_SW3__0__HSIOM_MASK 0x00000F00u
#define RELAY_SW3__0__HSIOM_SHIFT 8u
#define RELAY_SW3__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_SW3__0__INTR CYREG_GPIO_PRT2_INTR
#define RELAY_SW3__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_SW3__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define RELAY_SW3__0__MASK 0x04u
#define RELAY_SW3__0__PC CYREG_GPIO_PRT2_PC
#define RELAY_SW3__0__PC2 CYREG_GPIO_PRT2_PC2
#define RELAY_SW3__0__PORT 2u
#define RELAY_SW3__0__PS CYREG_GPIO_PRT2_PS
#define RELAY_SW3__0__SHIFT 2u
#define RELAY_SW3__DR CYREG_GPIO_PRT2_DR
#define RELAY_SW3__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define RELAY_SW3__DR_INV CYREG_GPIO_PRT2_DR_INV
#define RELAY_SW3__DR_SET CYREG_GPIO_PRT2_DR_SET
#define RELAY_SW3__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_SW3__INTR CYREG_GPIO_PRT2_INTR
#define RELAY_SW3__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define RELAY_SW3__INTSTAT CYREG_GPIO_PRT2_INTR
#define RELAY_SW3__MASK 0x04u
#define RELAY_SW3__PC CYREG_GPIO_PRT2_PC
#define RELAY_SW3__PC2 CYREG_GPIO_PRT2_PC2
#define RELAY_SW3__PORT 2u
#define RELAY_SW3__PS CYREG_GPIO_PRT2_PS
#define RELAY_SW3__SHIFT 2u

/* Clock_Beep */
#define Clock_Beep__CTRL_REGISTER CYREG_PERI_PCLK_CTL3
#define Clock_Beep__DIV_ID 0x00000045u
#define Clock_Beep__DIV_REGISTER CYREG_PERI_DIV_16_CTL5
#define Clock_Beep__PA_DIV_ID 0x000000FFu

/* Clock_Local */
#define Clock_Local__CTRL_REGISTER CYREG_PERI_PCLK_CTL7
#define Clock_Local__DIV_ID 0x00000041u
#define Clock_Local__DIV_REGISTER CYREG_PERI_DIV_16_CTL1
#define Clock_Local__PA_DIV_ID 0x000000FFu

/* Clock_Night */
#define Clock_Night__CTRL_REGISTER CYREG_PERI_PCLK_CTL5
#define Clock_Night__DIV_ID 0x00000042u
#define Clock_Night__DIV_REGISTER CYREG_PERI_DIV_16_CTL2
#define Clock_Night__PA_DIV_ID 0x000000FFu

/* PWM_Distict_cy_m0s8_tcpwm_1 */
#define PWM_Distict_cy_m0s8_tcpwm_1__CC CYREG_TCPWM_CNT1_CC
#define PWM_Distict_cy_m0s8_tcpwm_1__CC_BUFF CYREG_TCPWM_CNT1_CC_BUFF
#define PWM_Distict_cy_m0s8_tcpwm_1__COUNTER CYREG_TCPWM_CNT1_COUNTER
#define PWM_Distict_cy_m0s8_tcpwm_1__CTRL CYREG_TCPWM_CNT1_CTRL
#define PWM_Distict_cy_m0s8_tcpwm_1__INTR CYREG_TCPWM_CNT1_INTR
#define PWM_Distict_cy_m0s8_tcpwm_1__INTR_MASK CYREG_TCPWM_CNT1_INTR_MASK
#define PWM_Distict_cy_m0s8_tcpwm_1__INTR_MASKED CYREG_TCPWM_CNT1_INTR_MASKED
#define PWM_Distict_cy_m0s8_tcpwm_1__INTR_SET CYREG_TCPWM_CNT1_INTR_SET
#define PWM_Distict_cy_m0s8_tcpwm_1__PERIOD CYREG_TCPWM_CNT1_PERIOD
#define PWM_Distict_cy_m0s8_tcpwm_1__PERIOD_BUFF CYREG_TCPWM_CNT1_PERIOD_BUFF
#define PWM_Distict_cy_m0s8_tcpwm_1__STATUS CYREG_TCPWM_CNT1_STATUS
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMD CYREG_TCPWM_CMD
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK 0x02u
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT 1u
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK 0x200u
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT 9u
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK 0x2000000u
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT 25u
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK 0x20000u
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT 17u
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CTRL CYREG_TCPWM_CTRL
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK 0x02u
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT 1u
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE CYREG_TCPWM_INTR_CAUSE
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK 0x02u
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT 1u
#define PWM_Distict_cy_m0s8_tcpwm_1__TCPWM_NUMBER 1u
#define PWM_Distict_cy_m0s8_tcpwm_1__TR_CTRL0 CYREG_TCPWM_CNT1_TR_CTRL0
#define PWM_Distict_cy_m0s8_tcpwm_1__TR_CTRL1 CYREG_TCPWM_CNT1_TR_CTRL1
#define PWM_Distict_cy_m0s8_tcpwm_1__TR_CTRL2 CYREG_TCPWM_CNT1_TR_CTRL2

/* Pin_Distict */
#define Pin_Distict__0__DR CYREG_GPIO_PRT2_DR
#define Pin_Distict__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Pin_Distict__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Pin_Distict__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Pin_Distict__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define Pin_Distict__0__HSIOM_MASK 0x0F000000u
#define Pin_Distict__0__HSIOM_SHIFT 24u
#define Pin_Distict__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_Distict__0__INTR CYREG_GPIO_PRT2_INTR
#define Pin_Distict__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_Distict__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define Pin_Distict__0__MASK 0x40u
#define Pin_Distict__0__PC CYREG_GPIO_PRT2_PC
#define Pin_Distict__0__PC2 CYREG_GPIO_PRT2_PC2
#define Pin_Distict__0__PORT 2u
#define Pin_Distict__0__PS CYREG_GPIO_PRT2_PS
#define Pin_Distict__0__SHIFT 6u
#define Pin_Distict__DR CYREG_GPIO_PRT2_DR
#define Pin_Distict__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Pin_Distict__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Pin_Distict__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Pin_Distict__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_Distict__INTR CYREG_GPIO_PRT2_INTR
#define Pin_Distict__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Pin_Distict__INTSTAT CYREG_GPIO_PRT2_INTR
#define Pin_Distict__MASK 0x40u
#define Pin_Distict__PC CYREG_GPIO_PRT2_PC
#define Pin_Distict__PC2 CYREG_GPIO_PRT2_PC2
#define Pin_Distict__PORT 2u
#define Pin_Distict__PS CYREG_GPIO_PRT2_PS
#define Pin_Distict__SHIFT 6u

/* Clock_Distict */
#define Clock_Distict__CTRL_REGISTER CYREG_PERI_PCLK_CTL4
#define Clock_Distict__DIV_ID 0x00000043u
#define Clock_Distict__DIV_REGISTER CYREG_PERI_DIV_16_CTL3
#define Clock_Distict__PA_DIV_ID 0x000000FFu

/* Miscellaneous */
#define CY_PROJECT_NAME "MeshNodeC_SW"
#define CY_VERSION "PSoC Creator  3.3 CP3"
#define CYDEV_BANDGAP_VOLTAGE 1.200
#define CYDEV_BCLK__HFCLK__HZ 24000000U
#define CYDEV_BCLK__HFCLK__KHZ 24000U
#define CYDEV_BCLK__HFCLK__MHZ 24U
#define CYDEV_BCLK__SYSCLK__HZ 24000000U
#define CYDEV_BCLK__SYSCLK__KHZ 24000U
#define CYDEV_BCLK__SYSCLK__MHZ 24U
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PANTHER 19u
#define CYDEV_CHIP_DIE_PSOC4A 11u
#define CYDEV_CHIP_DIE_PSOC5LP 18u
#define CYDEV_CHIP_DIE_TMA4 2u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC4
#define CYDEV_CHIP_JTAG_ID 0x190F11A9u
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_MEMBER_4A 11u
#define CYDEV_CHIP_MEMBER_4C 16u
#define CYDEV_CHIP_MEMBER_4D 7u
#define CYDEV_CHIP_MEMBER_4E 4u
#define CYDEV_CHIP_MEMBER_4F 12u
#define CYDEV_CHIP_MEMBER_4G 2u
#define CYDEV_CHIP_MEMBER_4H 10u
#define CYDEV_CHIP_MEMBER_4I 15u
#define CYDEV_CHIP_MEMBER_4J 8u
#define CYDEV_CHIP_MEMBER_4K 9u
#define CYDEV_CHIP_MEMBER_4L 14u
#define CYDEV_CHIP_MEMBER_4M 13u
#define CYDEV_CHIP_MEMBER_4N 6u
#define CYDEV_CHIP_MEMBER_4O 5u
#define CYDEV_CHIP_MEMBER_4U 3u
#define CYDEV_CHIP_MEMBER_5A 18u
#define CYDEV_CHIP_MEMBER_5B 17u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_4J
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
#define CYDEV_CHIP_REV_PANTHER_ES0 0u
#define CYDEV_CHIP_REV_PANTHER_ES1 1u
#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REV_TMA4_ES 17u
#define CYDEV_CHIP_REV_TMA4_ES2 33u
#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
#define CYDEV_CHIP_REVISION_4G_ES 17u
#define CYDEV_CHIP_REVISION_4G_ES2 33u
#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4J_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
#define CYDEV_CONFIG_READ_ACCELERATOR 1
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_DEBUG_PROTECT_KILL 4
#define CYDEV_DEBUG_PROTECT_OPEN 1
#define CYDEV_DEBUG_PROTECT CYDEV_DEBUG_PROTECT_OPEN
#define CYDEV_DEBUG_PROTECT_PROTECTED 2
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DFT_SELECT_CLK0 8u
#define CYDEV_DFT_SELECT_CLK1 9u
#define CYDEV_HEAP_SIZE 0x80
#define CYDEV_IMO_TRIMMED_BY_USB 0u
#define CYDEV_IMO_TRIMMED_BY_WCO 0u
#define CYDEV_IS_EXPORTING_CODE 0
#define CYDEV_IS_IMPORTING_CODE 0
#define CYDEV_PROJ_TYPE 0
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LAUNCHER 5
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_STACK_SIZE 0x0200
#define CYDEV_USE_BUNDLED_CMSIS 1
#define CYDEV_VARIABLE_VDDA 1
#define CYDEV_VDDA 3.3
#define CYDEV_VDDA_MV 3300
#define CYDEV_VDDD 3.3
#define CYDEV_VDDD_MV 3300
#define CYDEV_WDT_GENERATE_ISR 0u
#define CYIPBLOCK_m0s8cpussv3_VERSION 1
#define CYIPBLOCK_m0s8csdv2_VERSION 1
#define CYIPBLOCK_m0s8ioss_VERSION 1
#define CYIPBLOCK_m0s8lcd_VERSION 2
#define CYIPBLOCK_m0s8lpcomp_VERSION 2
#define CYIPBLOCK_m0s8peri_VERSION 1
#define CYIPBLOCK_m0s8scb_VERSION 2
#define CYIPBLOCK_m0s8tcpwm_VERSION 2
#define CYIPBLOCK_m0s8wco_VERSION 1
#define CYIPBLOCK_s8srsslt_VERSION 1
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
